The present invention relates to a timing signal extracting circuit for a coded mark inversion (CMI) signal and, particularly, to a timing extracting circuit for such CMI signal containing CMI rule violation in a CMI code strain.
With an increased speed of information processing caused by recent development of information processing devices, improvement on efficiency and speed of data transmission between information processing devices have been requested. In view of these requests, the optical transmission has been utilized in which high speed data is transmitted through optical fibers. In general, in order to transmit data, the data is converted into a transmitting code train suitable for transmission through a transmission path such as optical fibers.
CMI code is one of these transmitting code trains, whose coding rule is as follow: that is, an input data "0" to be transmitted is converted into "01" and an input data "1" is converted alternatively into "00" and "11. On a decoding side, "01" is decoded to "0", a series of alternating "00" and "11", without "01" is decoded to "1" and otherwise be violation.
An example of violation is a sectioning information for indicating sections of data to be transmitted or other information such as those to be superimposed.
Japanese Patent Application Laid-open No. Hei 3-145834 discloses an example of a construction of a clock timing extracting circuit for a CMI signal train containing violation.
In the conventional construction of the timing extracting circuit for CMI code, however, it is based on that CMI code includes CMI coded signals "0" and "1" which occur at least twice preceeding its violation. Therefore, when a service data signal which is very low compared with a transmission speed of a main signal is transmitted by violation of the CMI code train, it is impossible to extract a timing exactly.